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ltc2413 1 sn2413 2413fs the ltc ? 2413 is a 2.7v to 5.5v simultaneous 50hz/60hz rejection micropower 24-bit differential ds analog to digital converter with an integrated oscillator, 2ppm inl and 0.16ppm rms noise. it uses delta-sigma technology and provides single cycle settling time for multiplexed applications. through a single pin, the ltc2413 can be configured for better than 87db input differential mode rejection over the range of 49hz to 61.2hz (50hz and 60hz 2% simultaneously), or it can be driven by an external oscillator for a user defined rejection frequency. the internal oscillator requires no external frequency setting components. the converter accepts any external differential reference voltage from 0.1v to v cc for flexible ratiometric and remote sensing measurement configurations. the full- scale differential input range is from C 0.5v ref to 0.5v ref . the reference common mode voltage, v refcm , and the input common mode voltage, v incm , may be indepen- dently set anywhere within the gnd to v cc range of the ltc2413. the dc common mode input rejection is better than 140db. the ltc2413 communicates through a flexible 3-wire digital interface which is compatible with spi and microwire tm protocols. n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain-gauge transducers n instrumentation n data acquisition n industrial process control n 6-digit dvms n products for international markets , ltc and lt are registered trademarks of linear technology corporation. n simultaneous 50hz/60hz rejection (87db minimum) n differential input and differential reference with gnd to v cc common mode range n 2ppm inl and no missing codes at 24 bits n 0.1ppm offset and 2.5ppm full-scale error n 0.16ppm noise n no latency: digital filter settles in a single cycle. n internal oscillatorno external components required n 24-bit adc in narrow ssop-16 package (so-8 footprint) n single supply 2.7v to 5.5v operation n low supply current (200 m a) and auto shutdown n pin compatible with ltc2410 24-bit no latency ds tm adc, with simultaneous 50hz/60hz rejection no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 3-wire spi interface 1 f 2.7v to 5.5v ltc2413 2413 ta01 = external clock source = internal osc/ simultaneous 50hz/60hz rejection input frequency (hz) 48 50 52 54 56 58 60 62 normal mode reection (db) 2413 ta02 ?0 ?5 ?0 ?5 100 105 110 115 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data applicatio s u features typical applicatio u descriptio u measured noise rejection from 48hz to 62.5hz
ltc2413 2 sn2413 2413fs absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics (notes 1, 2) order part number consult factory for parts specified with wider operating temperature ranges. supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) reference input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2413c ............................................... 0 c to 70 c ltc2413i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c t jmax = 125 c, q ja = 95 c/w ltc2413cgn ltc2413ign parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) l 24 bits integral nonlinearity 4.5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 1 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) l 2 14 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 5 ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, l 0.5 2.5 m v gnd in + = in C v cc , (note 13) offset error drift 2.5v ref + v cc , ref C = gnd, 10 nv/ c gnd in + = in C v cc positive full-scale error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.75 ? ref + , in C = 0.25 ? ref + positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.75 ? ref + , in C = 0.25 ? ref + negative full-scale error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.25 ? ref + , in C = 0.75 ? ref + negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 4.5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 3 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 3 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v 4 ppm of v ref output noise 5v v cc 5.5v, ref + = 5v, v ref C = gnd, 0.8 m v rms gnd in C = in + 5v, (note 12) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) gn part marking 2413 2413i top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd v cc ref + ref in + in gnd gnd gnd gnd f o sck sdo cs gnd gnd ltc2413 3 sn2413 2413fs symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage l gnd C 0.3v v cc + 0.3v v v in input differential voltage range l Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1v v v ref reference differential voltage range l 0.1 v cc v (ref + C ref C ) c s (in + )in + sampling capacitance 18 pf c s (in C )in C sampling capacitance 18 pf c s (ref + )ref + sampling capacitance 18 pf c s (ref C )ref C sampling capacitance 18 pf i dc_leak (in + )in + dc leakage current cs = v cc , in + = gnd l C10 1 10 na i dc_leak (in C )in C dc leakage current cs = v cc , in C = gnd l C10 1 10 na i dc_leak (ref + )ref + dc leakage current cs = v cc , ref + = 5v l C10 1 10 na i dc_leak (ref C )ref C dc leakage current cs = v cc , ref C = gnd l C10 1 10 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, l 130 140 db gnd in C = in + v cc input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 49hz to 61.2hz gnd in C = in + v cc , (note 7) input normal mode rejection (note 7) l 87 db 49hz to 61.2hz input normal mode rejection external oscillator l 87 db external clock f eosc /2560 14% input normal mode rejection external oscillator l 110 140 db external clock f eosc /2560 4% reference common mode 2.5v ref + v cc , gnd ref C 2.5v, l 130 140 db rejection dc v ref = 2.5v, in C = in + = gnd power supply rejection, dc ref + = 2.5v, ref C = gnd, in C = in + = gnd 120 db power supply rejection ref + = 2.5v, ref C = gnd, 120 db simultaneous 50hz/60hz 2% in C = in + = gnd, (note 7) co verter characteristics u a alog i put a u d refere ce uu u ltc2413 4 sn2413 2413fs symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 11) l 200 300 m a sleep mode cs = v cc (note 11) l 20 30 m a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 8) l 2.5 v sck 2.7v v cc 3.3v (note 8) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 8) l 0.8 v sck 2.7v v cc 5.5v (note 8) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 8) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 8) 10 pf sck v oh high level output voltage i o = C800 m a l v cc C 0.5v v sdo v ol low level output voltage i o = 1.6ma l 0.4 v sdo v oh high level output voltage i o = C800 m a (note 9) l v cc C 0.5v v sck v ol low level output voltage i o = 1.6ma (note 9) l 0.4 v sck i oz hi-z output leakage l C10 10 m a sdo digital i puts a d digital outputs uu power require e ts w u ltc2413 5 sn2413 2413fs note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to external conversion clock source with f eosc = 139800hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 139800hz 2% (external oscillator). note 8: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 9: the converter is in internal sck mode of operation such that the sck pin is used as digital output. note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses the internal oscillator. f o = 0v. note 12: the output noise includes the contribution of the internal calibration operations. note 13: guaranteed by design and test correlation. f eosc external oscillator frequency range l 2.56 2000 khz t heo external oscillator high period l 0.25 390 m s t leo external oscillator low period l 0.25 390 m s t conv conversion time f o = 0v l 146.71 ms external oscillator (note 10) l 20510/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 9) 17.5 khz external oscillator (notes 9, 10) f eosc /8 khz d isck internal sck duty cycle (note 9) l 45 55 % f esck external sck frequency range (note 8) l 2000 khz t lesck external sck low period (note 8) l 250 ns t hesck external sck high period (note 8) l 250 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 9, 11) l 1.80 1.83 1.86 ms external oscillator (notes 9, 10) l 256/f eosc (in khz) ms t dout_esck external sck 32-bit data output time (note 8) l 32/f esck (in khz) ms t 1 cs to sdo low z l 0 200 ns t2 cs - to sdo hi-z l 0 200 ns t3 cs to sck (note 9) l 0 200 ns t4 cs to sck - (note 8) l 50 ns t kqmax sck to sdo valid l 220 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units ti i g characteristics w u ltc2413 6 sn2413 2413fs typical perfor a ce characteristics uw total unadjusted error vs temperature (v cc = 2.7v, v ref = 2.5v) total unadjusted error vs temperature (v cc = 5v, v ref = 2.5v) total unadjusted error vs temperature (v cc = 5v, v ref = 5v) integral nonlinearity vs temperature (v cc = 2.7v, v ref = 2.5v) integral nonlinearity vs temperature (v cc = 5v, v ref = 2.5v) integral nonlinearity vs temperature (v cc = 5v, v ref = 5v) noise histogram (output rate = 52.5hz, v cc = 5v, v ref = 5v) noise histogram (output rate = 22.5hz, v cc = 5v, v ref = 5v) noise histogram (output rate = 6.83hz, v cc = 5v, v ref = 5v) v in (v) 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 tue (ppm of v ref ) 2413 g01 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 5v ref = gnd v ref = 5v v incm = 2.5v f o = gnd t a = 90 c t a = 25 c t a = 45 c v in (v) ? 0.5 0 0.5 1 tue (ppm of v ref ) 2413 g02 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 2.5v ref = gnd v ref = 2.5v v incm = 1.25v f o = gnd t a = 90 c t a = 25 c t a = 45 c v in (v) ? 0.5 0 0.5 1 tue (ppm of v ref ) 2413 g03 10 8 6 4 2 0 ? ? ? ? ?0 v cc = 2.7v ref + = 2.5v ref = gnd v ref = 2.5v v incm = 1.25v f o = gnd t a = 90 c t a = 25 c t a = 45 c v in (v) 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 inl error (ppm of v ref ) 2413 g04 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 5v ref = gnd v ref = 5v v incm = 2.5v f o = gnd t a = 45 c t a = 25 c t a = 90 c v in (v) ? 0.5 0 0.5 1 inl error (ppm of v ref ) 2413 g05 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 2.5v ref = gnd v ref = 2.5v v incm = 1.25v f o = gnd t a = 25 c t a = 45 c t a = 90 c v in (v) ? 0.5 0 0.5 1 inl error (ppm of v ref ) 2413 g06 10 8 6 4 2 0 ? ? ? ? ?0 v ref = 2.5v v incm = 1.25v f o = gnd v cc = 2.7v ref + = 2.5v ref = gnd t a = 25 c t a = 45 c t a = 90 c output code (ppm of v ref ) ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 number of readings (%) 2413 g07 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd t a = 25 c gaussian distribution m = 0.105ppm s = 0.153ppm output code (ppm of v ref ) ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 number of readings (%) 2413 g08 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = 460800hz t a = 25 c gaussian distribution m = 0.067ppm s = 0.151ppm output code (ppm of v ref ) 9.8 9.4 ? 8.6 8.2 7.8 7.4 7 6.6 number of readings (%) 2413 g09 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = 1075200hz t a = 25 c gaussian distribution m = 8.285ppm s = 0.311ppm ltc2413 7 sn2413 2413fs typical perfor a ce characteristics uw output code (ppm of v ref ) 1.6 0.8 0 0.8 1.6 number of readings (%) 2413 g10 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = gnd t a = 25 c gaussian distribution m = 0.033ppm s = 0.293ppm output code (ppm of v ref ) 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 number of readings (%) 2413 g11 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 460800hz t a = 25 c gaussian distribution m = 0.014ppm s = 0.292ppm output code (ppm of v ref ) 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 2.3 number of readings (%) 2413 g12 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 1075200hz t a = 25 c gaussian distribution m = 3.852ppm s = 0.326ppm output code (ppm of v ref ) 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 number of readings (%) 2413 g13 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = gnd t a = 25 c gaussian distribution m = 0.079ppm s = 0.298ppm output code (ppm of v ref ) 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 number of readings (%) 2413 g14 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 460800hz t a = 25 c gaussian distribution m = 0.177ppm s = 0.297ppm output code (ppm of v ref ) ?0 8.5 ? 5.5 ? 2.5 1 0.5 2 number of readings (%) 2413 g15 10 9 8 7 6 5 4 3 2 1 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 1075200hz t a = 25 c gaussian distribution m = 3.714ppm s = 1.295ppm output code (ppm of v ref ) ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 number of readings (%) 2413 g16 12 10 8 6 4 2 0 adc consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd t a = 25 c gaussian distribution m = 0.101837ppm s = 0.154515ppm time (hours) 0 5 10 15 20 25 30 35 40 45 50 55 60 adc reading (ppm of v ref ) 2413 g17 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 v cc = 5v v ref = 5v v in = 0v f o = gnd t a = 25 c ref + = 5v ref = gnd in + = 2.5v in = 2.5v input differential voltage (v) 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 rms noise (ppm of v ref ) 2413 g18 0.5 0.4 0.3 0.2 0.1 0 v cc = 5v v ref = 5v ref + = 5v ref = gnd v incm = 2.5v f o = gnd t a = 25 c noise histogram (output rate = 52.5hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 22.5hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 6.83hz v cc = 5v, v ref = 2.5v) noise histogram (output rate = 52.5hz, v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 22.5hz, v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 6.83hz v cc = 2.7v, v ref = 2.5v) rms noise vs input differential voltage consecutive adc readings vs time long-term noise histogram (time = 60 hrs, v cc = 5v, v ref = 5v) ltc2413 8 sn2413 2413fs typical perfor a ce characteristics uw rms noise vs v cc rms noise vs temperature (t a ) rms noise vs v incm offset error vs temperature (t a ) offset error vs v incm rms noise vs v ref + full-scale error vs temperature (t a ) offset error vs v ref offset error vs v cc v incm (v) ?.5 0 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 rms noise (nv) 2413 g19 850 825 800 775 750 725 700 675 650 v cc = 5v ref + = 5v ref = gnd v ref = 5v in + = v incm in = v incm v in = 0v f o = gnd t a = 25 c temperature ( c) rms noise (nv) 2413 g20 850 825 800 775 750 725 700 675 650 ?0 ?5 0 25 50 75 100 v cc = 5v ref + = 5v ref = gnd in + = 2.5v in = 2.5v v in = 0v f o = gnd v cc (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 rms noise (nv) 2413 g21 850 825 800 775 750 725 700 675 650 ref + = 2.5v ref = gnd v ref = 2.5v in + = gnd in = gnd f o = gnd t a = 25 c v ref (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 rms noise (nv) 2413 g22 850 825 800 775 750 725 700 675 650 v cc = 5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c v incm (v) ?.5 0 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 offset error (ppm of v ref ) 2413 g23 0.3 0.2 0.1 0 0.1 0.2 0.3 v cc = 5v ref + = 5v ref = gnd v ref = 5v in + = v incm in = v incm v in = 0v f o = gnd t a = 25 c temperature ( c) ?0 ?5 0 25 50 75 100 offset error (ppm of v ref ) 2413 g24 0.3 0.2 0.1 0 0.1 0.2 0.3 v cc = 5v ref + = 5v ref = gnd in + = 2.5v in = 2.5v v in = 0v f o = gnd v cc (v) offset error (ppm of v ref ) 2413 g25 0.3 0.2 0.1 0 0.1 0.2 0.3 ref + = 2.5v ref = gnd v ref = 2.5v in + = gnd in = gnd f o = gnd t a = 25 c 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v ref (v) offset error (ppm of v ref ) 2413 g26 0.3 0.2 0.1 0 0.1 0.2 0.3 v cc = 5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 temperature ( c) +full-scale error (ppm of v ref ) 2413 g27 3 2 1 0 ? ? ? ?5 ?0 ?5 0 15 30 45 60 75 90 v cc = 5v ref + = 5v ref = gnd in + = 2.5v in = gnd f o = gnd ltc2413 9 sn2413 2413fs typical perfor a ce characteristics uw C full-scale error vs temperature (t a ) + full-scale error vs v ref + full-scale error vs v cc psrr vs frequency at v cc C full-scale error vs v ref C full-scale error vs v cc psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc v cc (v) +full-scale error (ppm of v ref ) 2413 g28 3 2 1 0 ? ? ? ref + = 2.5v ref = gnd v ref = 2.5v in + = 1.25v in = gnd f o = gnd t a = 25 c 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v ref (v) +full-scale error (ppm of v ref ) 2413 g29 3 2 1 0 ? ? ? v cc = 5v ref + = v ref ref = gnd in + = 0.5 ?ref + in = gnd f o = gnd t a = 25 c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 temperature ( c) full-scale error (ppm of v ref ) 2413 g30 3 2 1 0 ? ? ? ?5 ?0 ?5 0 15 30 45 60 75 90 v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd v cc (v) full-scale error (ppm of v ref ) 2413 g31 3 2 1 0 ? ? ? ref + = 2.5v ref = gnd v ref = 2.5v in + = gnd in = 1.25v f o = gnd t a = 25 c 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v ref (v) full-scale error (ppm of v ref ) 2413 g32 3 2 1 0 ? ? ? v cc = 5v ref + = v ref ref = gnd in + = gnd in = 0.5 ?ref + f o = gnd t a = 25 c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 frequency at v cc (hz) rejection (db) 2413 g33 0 ?0 ?0 ?0 ?0 100 120 140 0.01 0.1 1 10 100 v cc = 4.1v dc 1.4v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c frequency at v cc (hz) rejection (db) 2413 g34 0 ?0 ?0 ?0 ?0 100 120 140 020 40 60 80 100 120 140 160 180 200 220 v cc = 4.1v dc 1.4v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c frequency at v cc (hz) rejection (db) 2413 g35 0 ?0 ?0 ?0 ?0 100 120 140 1 10 100 1k 10k 100k 1m ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c 0 ?0 ?0 ?0 ?0 100 120 140 frequency at v cc (hz) rejection (db) 2413 g36 13900 13950 14000 14050 14100 v cc = 4.1v dc 0.7v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c ltc2413 10 sn2413 2413fs gnd (pins 1, 7, 8, 9, 10, 15, 16): ground. multiple ground pins internally connected for optimum ground current flow and v cc decoupling. connect each one of these pins to a ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. v cc (pin 2): positive supply voltage. bypass to gnd (pin 1) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. ref + (pin 3), ref C (pin 4): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 5), in C (pin 6): differential analog input. the voltage on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits, the converter bipolar input range (v in = in + C in C ) extends from C0.5 ? (v ref ) to 0.5 ? (v ref ). outside this input range, the converter produces unique overrange and underrange output codes. cs (pin 11): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion, the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 12): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 13): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface clock during the data output period. a weak internal pull- up is automatically activated in internal serial clock op- eration mode. the serial clock operation mode is deter- mined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. f o (pin 14): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to gnd (f o = 0v), the converter uses its internal oscillator and the digital filter rejects 50hz and 60hz simultaneously. when the f o pin is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter has 87db minimum rejection in the range f eosc /2560 14% and 110db minimum rejection at f eosc /2560 4%. pi fu ctio s uuu typical perfor a ce characteristics uw temperature ( c) supply current ( a) 2413 g39 23 22 21 20 19 18 17 16 ?5 ?0 ?5 0 15 30 45 60 75 90 f o = gnd cs = v cc sck = nc sdo = nc v cc = 5.5v v cc = 2.7v v cc = 4.1v sleep current vs temperature (t a ) output data rate (readings/sec) supply current ( a) 2413 g38 1100 1000 900 800 700 600 500 400 300 200 100 010 20 30 40 50 60 70 80 90 100 v cc = 5v ref + = 5v ref = gnd in + = gnd in = gnd t a = 25 c f o = external osc cs = gnd sck = nc sdo = nc temperature ( c) supply current ( a) 2413 g37 220 210 200 190 180 170 160 ?5 ?0 ?5 0 15 30 45 60 75 90 f o = gnd cs = gnd sck = nc sdo = nc v cc = 5.5v v cc = 4.1v v cc = 2.7v conversion current vs output data rate conversion current vs temperature (t a ) ltc2413 11 sn2413 2413fs test circuits applicatio s i for atio wu u u fu ctio al block diagra uu w figure 2. ltc2413 state transition diagram converter operation converter operation cycle the ltc2413 is a low power, delta-sigma analog-to- digital converter with an easy to use 3-wire serial interface. its operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see figure 2). the 3-wire interface consists of serial data output (sdo), serial clock (sck) and chip select (cs). initially, the ltc2413 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced by an order of magnitude. the part remains in the sleep state as long as cs is high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc in + in sdo sck ref + ref cs f o (int/ext) 2413 fd ? + 1.69k sdo 2413 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc 1.69k sdo 2413 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf convert sleep data output 2413 f02 true false cs = low and sck figure 1. functional block diagram ltc2413 12 sn2413 2413fs once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result. the data output corresponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2413 offers several flexible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is de- signed to simultaneously reject line frequencies of 50hz and 60hz plus their harmonics. the filter rejection perfor- mance is directly related to the accuracy of the converter system clock. the ltc2413 incorporates a highly accu- rate on-chip oscillator. this eliminates the need for exter- nal frequency setting components such as crystals or oscillators. the ltc2413 achieves a minimum of 87db over the range of 49hz to 61.2hz. ease of use the ltc2413 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. the ltc2413 performs offset and full-scale calibrations in every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation de- scribed above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with re- spect to time, supply voltage change and temperature drift. power-up sequence the ltc2413 automatically enters an internal reset state when the power supply voltage v cc drops below approxi- mately 2.2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selec- tion. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2413 starts a normal conversion cycle and follows the succession of states described above. the first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range this converter accepts a truly differential external refer- ence voltage. the absolute/common mode voltage speci- fication for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2413 can accept a differential reference voltage from 0.1v to v cc . the converter output noise is deter- mined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effective resolution. on the other hand, a reduced reference voltage will im- prove the converters overall inl performance. a reduced reference voltage will also improve the converter perfor- mance when operated with an external conversion clock (external f o signal) at substantially higher output data rates (see the output data rate section). applicatio s i for atio wu u u ltc2413 13 sn2413 2413fs input voltage range the analog input is truly differential with an absolute/ common mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2413 converts the bipolar differential input signal, v in = in + C in C , from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. input signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + and in C pins without affecting the perfor- mance of the device. in the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. the effect of the series resistance on the converter accuracy can be evalu- ated from the curves presented in the input current/ reference current sections. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. output data format the ltc2413 serial output data stream is 32 bits long. the first 3 bits represent status information indicating the sign and conversion state. the next 24 bits are the conversion result, msb first. the remaining 5 bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. the third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). bit 31 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2413 status bits bit 31 bit 30 bit 29 bit 28 input range eoc dmy sig msb v in 3 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0000 bits 28-5 are the 24-bit conversion result msb first. bit 5 is the least significant bit (lsb). bits 4-0 are sub lsbs below the 24-bit level. bits 4-0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and any externally generated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the first rising edge of sck. bit 30 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched applicatio s i for atio wu u u ltc2413 14 sn2413 2413fs on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corre- sponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. simultaneous frequency rejection the ltc2413 internal oscillator provides better than 87db normal mode rejection over the range of 49hz to 61.2hz as shown in figure 4. for this simultaneous 50hz/60hz rejection, f o should be connected to gnd. when a fundamental rejection frequency different from the range 49hz to 61.2hz is required or when the converter must be sychronized with an outside source, the ltc2413 can operate with an external conversion clock. the conveter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods, t heo and t leo , are observed. table 2. ltc2413 output data format differential input voltage bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 0 v in * eoc dmy sig msb v in * 3 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . figure 3. output data timing applicatio s i for atio wu u u msb sig ? 1 2 3 4 5 262732 bit 0 bit 27 bit 5 lsb 24 bit 28 bit 29 bit 30 sdo sck cs eoc bit 31 sleep data output conversion 2413 f03 hi-z ltc2413 15 sn2413 2413fs while operating with an external conversion clock of a frequency f eosc , the ltc2413 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4%. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 5. whenever an external clock is not present at the f o pin the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2413 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 summarizes the duration of each state and the achievable output data rate as a function of f o . serial interface pins the ltc2413 transmits the conversion results and re- ceives the start of conversion command through a syn- chronous 3-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. table 3. ltc2413 state duration state operating mode duration convert internal oscillator f o = low 147ms, output data rate 6.8 readings/s simultaneous 50hz/60hz rejection external oscillator f o = external oscillator 20510/f eosc s, output data rate f eosc /20510 readings/s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = low and sck data output internal serial clock f o = low as long as cs = low but not longer than 1.83ms (internal oscillator) (32 sck cycles) f o = external oscillator with as long as cs = low but not longer than 256/f eosc ms frequency f eosc khz (32 sck cycles) external serial clock with as long as cs = low but not longer than 32/f sck ms frequency f sck khz (32 sck cycles) figure 5. ltc2413 normal mode rejection when using an external oscillator of frequency f eosc applicatio s i for atio wu u u differential input signal frequency deviation from notch frequency f eosc /2560(%) 12 8 404812 normal mode rejection (db) 2413 f05 ?0 ?5 ?0 ?5 100 105 110 115 120 125 130 135 140 48 50 52 54 56 58 60 62 differential input signal frequency (hz) normal mode reection ratio (db) 2413 f04 ?0 ?0 100 100 120 130 140 figure 4. ltc2413 normal mode rejection when using an internal oscillator ltc2413 16 sn2413 2413fs applicatio s i for atio wu u u serial clock input/output (sck) the serial clock signal present on sck (pin 13) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2413 creates its own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or floating at power- up or during this transition, the converter enters the inter- nal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo (pin 12), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 11) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = low. chip select input (cs) the active low chip select, cs (pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2413 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with cs=low). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . tying a capacitor to cs will reduce the output rate and power dissipation by a factor proportional to the capacitors value, see figures 13 to 15. serial interface timing modes the ltc2413s 3-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/external serial clock, 2- or 3-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. refer to table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 6. table 4. ltc2413 interface timing modes configuration sck source conversion cycle control data output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 6, 7 external sck, 2-wire i/o external sck sck figure 8 internal sck, single cycle conversion internal cs cs figures 9, 10 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 11 internal sck, autostart conversion internal c ext internal figure 12 ltc2413 17 sn2413 2413fs applicatio s i for atio wu u u the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis- ter. the device remains in the sleep state until the first rising edge of sck is seen while cs is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the 32nd falling edge of sck, see figure 7. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. this is useful for sys- tems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 8. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 0.5ms after v cc exceeds 2.2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. figure 6. external serial clock, single cycle operation eoc bit 31 sdo sck (external) cs test eoc sub lsb msb sig bit 0 lsb bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2413 f06 conversion = external oscillator = internal osc/simultaneous 50hz/60hz rejection hi-z hi-z hi-z test eoc test eoc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 1 f 2.7v to 5.5v ltc2413 3-wire spi interface ltc2413 18 sn2413 2413fs applicatio s i for atio wu u u since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion enters the low power sleep state. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the first rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 32nd falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 9. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the low power sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 26 m s if the device is using its internal oscillator (f 0 = logic low). if f o is driven by an external oscillator of frequency f eosc , figure 7. external serial clock, reduced data output length sdo sck (external) cs data output conversion sleep sleep test eoc test eoc data output hi-z hi-z hi-z conversion 2413 f07 msb sig bit 8 bit 27 bit 9 bit 28 bit 29 bit 30 eoc bit 31 bit 0 eoc hi-z test eoc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 3-wire spi interface 1 f 2.7v to 5.5v ltc2413 = external oscillator = internal osc/simultaneous 50hz/60hz rejection ltc2413 19 sn2413 2413fs applicatio s i for atio wu u u figure 8. external serial clock, cs = 0 operation figure 9. internal serial clock, single cycle operation eoc bit 31 sdo sck (external) cs msb sig bit 0 lsb 24 bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2413 f08 conversion v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 2-wire i/o 1 f 2.7v to 5.5v ltc2413 = external oscillator = internal osc/simultaneous 50hz/60hz rejection sdo sck (internal) cs msb sig bit 0 lsb 24 bit 5 test eoc bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 sleep data output conversion conversion 2413 f09 |